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december 1992 order number: 271074-006 military i387 tm math coprocessor y high performance 80-bit internal architecture y implements ansi/ieee standard 754- 1985 for binary floating-point arithmetic y five to seven times m8087/m80287 performance y upward object-code compatible from m8087 and m80287 y expands i386 tm microprocessor data types to include 32-, 64-, 80-bit floating point, 32-, 64-bit integers and 18-digit bcd operands y directly extends i386 processor instruction set to include trigonometric, logarithmic, exponential and arithmetic instructions for all data types y full-range transcendental operations for sine, cosine, tangent, arctangent and logarithm y built-in exception handling y operates independently of real, protected and virtual-8086 modes of the i386 microprocessor y eight 80-bit numeric registers, usable as individually addressable general registers or as a register stack y available in 68-pin pga package and 68-lead ceramic quad flat pack (see packaging spec: order y 231369) y available in three product grades: e mil-std-883, b 55 cto a 125 c(t c ) e military temperature only, b 55 cto a 125 c(t c ) e extended temperature, b 40 cto a 110 c(t c ) the intel i387 is a high-performance numerics processor extension that extends the i386 microprocessor architecture with floating point, extended integer and bcd data types. the i386/i387 processors' computing system fully conforms to the ansi/ieee floating-point standard. using a numerics oriented architecture, the i387 processor adds over seventy mnemonics to the i386/i387 processor instruction set, making the i386/i387 processor a complete solution for high-performance numerics processing. the i387 microprocessor is imple- mented with 1.5 micron, high-speed chmos technology and packaged in a 68-pin ceramic pin grid array (pga) package and a 68-pin ceramic quad flat pack package. the i386/i387 processor combination is upward object-code compatible from the i386/80287, 80286/80287 and 8086/8087 computing systems. 271074 1 figure 0.1. i387 tm math coprocessor block diagram
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military i387 tm math coprocessor contents page 1.0 functional description 4 2.0 programming interface 5 2.1 data types 5 2.2 numeric operands 5 2.3 register set 7 2.3.1 data registers 7 2.3.2 tag word 7 2.3.3 status word 8 2.3.4 instruction and data pointers 11 2.3.5 control word 13 2.4 interrupt description 13 2.5 exception handling 14 2.6 initialization 14 2.7 m8087 and m80287 compatibility 15 2.7.1 general differences 15 2.7.2 exceptions 16 3.0 hardware interface 16 3.1 signal description 16 3.1.1 m80386 clock 2 (386clk2) 20 3.1.2 m80387 clock 2 (387clk2) 20 3.1.3 m80387 clocking mode (ckm) 20 3.1.4 system reset (resetin) 20 3.1.5 processor extension request (pereq) 20 3.1.6 busy status (busy ) 20 3.1.7 error status (error ) 20 3.1.8 data pins (d31 d0) 21 3.1.9 write/read bus cycle (w/r ) 21 3.1.10 address strobe (ads ) 21 3.1.11 bus ready input (ready ) 21 contents page 3.1.12 ready output (readyo ) 21 3.1.13 status enable (sten) 21 3.1.14 npx select y 1 (nps1 ) 21 3.1.15 npx select y 2 (nps2 ) 21 3.1.16 command (cmd0 ) 21 3.2 processor architecture 21 3.2.1 bus control logic 22 3.2.2 data interface and control unit 22 3.2.3 floating point unit 22 3.3 system configuration 22 3.3.1 bus cycle tracking 23 3.3.2 i387 tm npx addressing 23 3.3.3 function selection 23 3.3.4 cpu/npx synchronization 23 3.3.5 synchronous or asynchronous modes 24 3.3.6 automatic bus cycle termination 24 3.4 bus operation 24 3.4.1 nonpipelined bus cycles 25 3.4.1.1 write cycle 25 3.4.1.2 read cycle 25 3.4.2 pipelined bus cycles 26 3.4.3 bus cycles of mixed type 27 3.4.4 busy and pereq timing relationship 27 5.0 electrical data 29 5.1 absolute maximum ratings 29 5.2 dc characteristics 30 5.3 ac characteristics 31 6.0 i387 tm numerics coprocessor extensions to the i386 tm microprocessor instruction set 36 appendix a a-1 3
military i387 tm math coprocessor i386 tm microprocessor registers general registers 31 15 0 eax ax ah al ebx bx bh bl ecx cx ch cl edx dx dh dl esi si edi di ebp bp esp sp segment registers 15 0 cs ss ds es fs gs 31 0 eip eflags l i387 tm numeric processor data registers l tag field l 79 78 64 63 0 1 0 l l r0 sign exponent significand l r1 l r2 l l r3 l r4 l r5 l l r6 l r7 l l l 15 0 47 0 l control register instruction pointer (in m80386) l status register data pointer (in m80386) l l tag word l l l l l l l l figure 1.1. i386 tm /i387 tm processors register set 1.0 functional description the i387 numeric processor extension (npx) pro- vides arithmetic instructions for a variety of numeric data types in i386/i387 processor systems. it also executes numerous built-in transcendental functions (e.g. tangent, sine, cosine, and log functions). the i387 microprocessor effectively extends the register and instruction set of an i386 processor system for existing data types and adds several new data types as well. figure 1.1 shows the model of registers visi- ble to i386/i387 processor programs. essentially, the i387 npx can be treated as an additional re- source or an extension to the i386 microprocessor. the i386 microprocessor together with an i387 npx can be used as a single unified system. the i387 npx works the same whether the i386 mi- croprocessor is executing in real-address mode, pro- tected mode, or virtual-m8086 mode. all memory ac- cess is handled by the i386 processor; the i387 npx merely operates on instructions and values passed to it by the i386 processor. therefore, the i387 npx is not sensitive to the processing mode of the i386 microprocessor. in real-address mode and virtual-8086 mode, the i386/i387 processor combination is completely up- ward compatible with software for m8086/m8087, m80286/m80287 real-address mode, and i386/m80287 processor real-address mode sys- tems. in protected mode, the i386/i387 processor combi- nation is completely upward compatible with soft- ware for m80286/m80287 protected mode, and i386/m80287 processor protected mode systems. the only differences of operation that may appear when m8086/m8087 programs are ported to a pro- tected-mode i386/i387 microprocessor system ( not using virtual-m8086 mode), is in the format of oper- ands for the administrative instructions fldenv, fstenv, frstor and fsave. these instructions are normally used only by exception handlers and operating systems, not by applications programs. the i387 npx contains three functional units that can operate in parallel to increase system perform- ance. the i386 microprocessor can be transferring commands and data to the i387 npx's bus control logic for the next instruction while the i387 npx's floating-point unit is performing the current numeric instruction. 4
military i387 tm math coprocessor 2.0 programming interface the i387 coprocessor adds to an i386 processor system additional data types, registers, instructions, and interrupts specifically designed to facilitate high- speed numerics processing. to use the i387 coproc- essor requires no special programming tools, be- cause all new instructions and data types are direct- ly supported by the i386 microprocessor assembler and compilers for high-level languages. all m8086/m8088 development tools that support the m8087 can also be used to develop software for the i386/i387 processors in real-address mode or virtu- al-m8086 mode. all m80286 development tools that support the m80287 can also be used to develop software for the i386/i387 processors. all communication between the i386 microprocessor and the i387 npx is transparent to applications soft- ware. the cpu automatically controls the i387 npx whenever a numerics instruction is executed. all physical memory and virtual memory of the cpu are available for storage of the instructions and oper- ands of programs that use the i387 npx. all memory addressing modes, including use of displacement, base register, index register, and scaling, are avail- able for addressing numerics operands. section 6 at the end of this data sheet lists by class the instructions that the i387 npx adds to the in- struction set of an i386 microprocessor system. 2.1 data types table 2.1 lists the seven data types that the i387 npx supports and presents the format for each type. operands are stored in memory with the least signifi- cant digit at the lowest memory address. programs retrieve these values by generating the lowest ad- dress. for maximum system performance, all oper- ands should start at physical-memory addresses evenly divisible by four (doubleword boundaries); op- erands may begin at any other addresses, but will require extra memory cycles to access the entire op- erand. internally, the i387 coprocessor holds all numbers in the extended-precision real format. instructions that load operands from memory automatically convert operands represented in memory as 16-, 32-, or 64- bit integers, 32- or 64-bit floating-point numbers, or 18-digit packed bcd numbers into extended-preci- sion real format. instructions that store operands in memory perform the inverse type conversion. 2.2 numeric operands a typical npx instruction accepts one or two oper- ands and produces a single result. in two-operand instructions, one operand is the contents of an npx register, while the other may be a memory location. the operands of some instructions are predefined; for example fsqrt always takes the square root of the number in the top stack element. 5
military i387 tm math coprocessor table 2.1. i387 tm npx data type representation in memory 271074 2 notes: (1) s e sign bit (0 e positive, 1 e negative) (2) d n e decimal digit (two per byte) (3) x e bits have no significance; i387 npx ignores when loading, zeros when storing (4) u e position of implicit binary point (5) i e integer bit of significand; stored in temporary real, implicit in single and double precision (6) exponent bias (normalized values): single: 127 (7fh) double: 1023 (3ffh) extended real: 16383 (3fffh) (7) packed bcd: ( b 1) s (d 17 ...d 0 ) (8) real: ( b 1) s (2 e-bias )(f 0 f 1 ...) 6
military i387 tm math coprocessor 15 0 tag (7) tag (6) tag (5) tag (4) tag (3) tag (2) tag (1) tag (0) note: the index i of tag(i) is not top-relative. a program typically uses the ``top'' field of status word to determine which tag(i) field refers to logical top of stack. tag values: 00 e valid 01 e zero 10 e qnan, snan, infinity, denormal and unsupported formats 11 e empty figure 2.1. i387 tm npx tag word 2.3 register set figure 1.1 shows the i387 npx register set. when an i387 npx is present in a system, programmers may use these registers in addition to the registers normally available on the i386 processor. 2.3.1 data registers i387 processor computations use the i387 npx's data registers. these eight 80-bit registers provide the equivalent capacity of twenty 32-bit registers. each of the eight data registers in the i387 npx is 80 bits wide and is divided into ``fields'' corresponding to the npxs extended-precision real data type. the i387 npx register set can be accessed either as a stack, with instructions operating on the top one or two stack elements, or as a fixed register set, with instructions operating on explicitly designated regis- ters. the top field in the status word identifies the current top-of-stack register. a ``push'' operation decrements top by one and loads a value into the new top register. a ``pop'' operation stores the value from the current top register and then increments top by one. like i386 microprocessor stacks in memory, the i387 npx register stack grows ``down'' toward lower-addressed registers. instructions may address the data registers either implicitly or explicitly. many instructions operate on the register at the top of the stack. these instruc- tions implicitly address the register at which top points. other instructions allow the programmer to explicitly specify which register to user. this explicit register addressing is also relative to top. 2.3.2 tag word the tag word marks the content of each numeric data register, as figure 2.1 shows. each two-bit tag represents one of the eight numerics registers. the principal function of the tag word is to optimize the npxs performance and stack handling by making it possible to distinguish between empty and nonemp- ty register locations. it also enables exception han- dlers to check the contents of a stack location with- out the need to perform complex decoding of the actual data. 7
military i387 tm math coprocessor 271074 3 es is set if any unmasked exception bit is set; cleared otherwise. see table 2.2 for interpretation of condition code. top values: 000 e register 0 is top of stack 001 e register 1 is top of stack # # # 111 e register 7 is top of stack for definitions of exceptions, refer to the section entitled ``exception handling'' figure 2.2. i387 tm npx status word 2.3.3 status word the 16-bit status word (in the status register) shown in figure 2.2 reflects the overall state of the m80387. it may be read and inspected by cpu code. bit 15, the b-bit (busy bit) is included for m8087 compatibility only. it reflects the contents of the es bit (bit 7 of the status word), not the status of the busy output of i387/m80287 processors. bits 13 11 (top) point to the m80387 register that is the current top-of-stack. the four numeric condition code bits (c 3 c 0 ) are similar to the flags in a cpu; instructions that per- form arithmetic operations update these bits to re- flect the outcome. the effects of these instructions on the condition code are summarized in tables 2.2 through 2.5. bit 7 is the error summary (es) status bit. this bit is set if any unmasked exception bit is set; it is clear otherwise. if this bit is set, the error signal is as- serted. bit 6 is the stack flag (sf). this bit is used to distin- guish invalid operations due to stack overflow or un- derflow from other kinds of invalid operations. when sf is set, bit 9 (c 1 ) distinguishes between stack overflow (c 1 e 1) and underflow (c 1 e 0). figure 2.2 shows the six exception flags in bits 5 0 of the status word. bits 5 0 are set to indicate that the i387 npx has detected an exception while exe- cuting an instruction. a later section entitled ``excep- tion handling'' explains how they are set and used. note that when a new value is loaded into the status word by the fldenv or frstor instruction, the value of es (bit 7) and its reflection in the b-bit (bit 15) are not derived from the values loaded from memory but rather are dependent upon the values of the exception flags (bits 5 0) in the status word and their corresponding masks in the control word. if es is set in such a case, the error output of the i387 npx is activated immediately. 8
military i387 tm math coprocessor table 2.2. condition code interpretation instruction c0 (s) c3 (z) c1 (a) c2 (c) fprem, fprem1 three least significant bits reduction (see table 2.3) of quotient 0 e complete q2 q0 q1 1 e incomplete or o/u fcom, fcomp, fcompp, ftst, result of comparison zero operand is not fucom, fucomp, (see table 2.4) or o/u comparable fucompp, ficom, (table 2.4) ficomp fxam operand class sign operand class (see table 2.5) or o/u (table 2.5) fchs, fabs, fxch, finctop, fdectop, zero constant loads, undefined undefined fxtract, fld, or o/u fild, fbld, fstp (ext real) fist, fbstp, frndint, fst, fstp, fadd, fmul, roundup fdiv, fdivr, undefined undefined fsub, fsubr, or o/u fscale, fsqrt, fpatan, f2xm1, fyl2x, fyl2xp1 fptan, fsin roundup reduction fcos, fsincos undefined or o/u ,0 e complete undefined 1 e incomplete if c2 e 1 fldenv, frstor each bit loaded from memory fldcw, fstenv, fstcw, fstsw, undefined fclex, finit, fsave o/u when both ie and sf bits of status word are set, indicating a stack exception, this bit distinguishes between stack overflow (c1 e 1) and underflow (c1 e 0). reduction if fprem or fprem1 produces a remainder that is less than the modulus, reduction is complete. when reduction is incomplete the value at the top of the stack is a partial remainder, which can be used as input to further reduction. for fptan, fsin, fcos, and fsincos, the reduction bit is set if the operand at the top of the stack is too large. in this case the original operand remains at the top of the stack. roundup when the pe bit of the status word is set, this bit indicates whether the last rounding in the instruction was upward. undefined do not rely on finding any specific value in these bits. 9
military i387 tm math coprocessor table 2.3. condition code interpretation after fprem and fprem1 instructions condition code interpretation after fprem and fprem1 c2 c3 c1 c0 incomplete reduction: 1 x x x further interaction required for complete reduction q1 q0 q2 q mod8 000 0 010 1 complete reduction: 0 100 2 c0, c3, c1 contain three least 110 3 significant bits of quotient 001 4 011 5 101 6 111 7 table 2.4. condition code resulting from comparison order c3 c2 c0 top l operand 0 0 0 top k operand 0 0 1 top e operand 1 0 0 unordered 1 1 1 table 2.5. condition code defining operand class c3 c2 c1 c0 value at top 0000 a unsupported 0001 a nan 0010 b unsupported 0011 b nan 0100 a normal 0101 a infinity 0110 b normal 0111 b infinity 1000 a 0 1001 a empty 1010 b 0 1011 b empty 1100 a denormal 1110 b denormal 10
military i387 tm math coprocessor 2.3.4 instruction and data pointers because the npx operates in parallel with the cpu, any errors detected by the npx may be reported after the cpu has executed the esc instruction which caused it. to allow identification of the failing numeric instruction, the i386/i387 processor combi- nation contains two pointer registers that supply the address of the failing numeric instruction and the ad- dress of its numeric memory operand (if appropri- ate). the instruction and data pointers are provided for user-written error handlers. these registers are ac- tually located in the i386 microprocessor, but appear to be located in the i387 npx because they are ac- cessed by the esc instructions fldenv, fstenv, fsave, and frstor. (in the m8086/m8087 and m80286/m80287, these registers are located in the npx.) whenever the i386 processor decodes a new esc instruction, it saves the address of the in- struction (including any prefixes that may be pres- ent), the address of the operand (if present), and the opcode. the instruction and data pointers appear in one of four formats depending on the operating mode of the i386 processor (protected mode or real-address mode) and depending on the operand-size attribute in effect (32-bit operand or 16-bit operand). when the i386 microprocessor is in virtual-m8086 mode, the real-address mode formats are used. (see fig- ures 2.3 through 2.6.) the esc instructions fldenv, fstenv, fsave, and frstor are used to transfer these values between the m80386 regis- ters and memory. note that the value of the data pointer is undefined if the prior esc instruction did not have a memory operand. 32-bit protected mode format 31 23 15 7 0 reserved control word 0 reserved status word 4 reserved tag word 8 ip offset c 00000 opcode 10..0 cs selector 10 data operand offset 14 reserved operand selector 18 figure 2.3. protected mode i387 tm npx instruction and data pointer image in memory, 32-bit format 11
military i387 tm math coprocessor 32-bit real-address mode format 31 23 15 7 0 reserved control word 0 reserved status word 4 reserved tag word 8 reserved instruction pointer 15..0 c 0000 instruction pointer 31..16 0 opcode 10..0 10 reserved operand pointer 15..0 14 0000 operand pointer 31..16 0000 00000000 18 figure 2.4. real mode i387 tm npx instruction and data pointer image in memory, 32-bit format 16-bit protected mode format 15 7 0 control word 0 status word 2 tag word 4 ip offset 6 cs selector 8 operand offset a operand selector c figure 2.5. protected mode i387 tm npx instruction and data pointer image in memory, 16-bit format 16-bit real-address mode and virtual-m8086 mode format 15 7 0 control word 0 status word 2 tag word 4 instruction pointer 15..0 6 ip19.16 0 opcode 10..0 8 operand pointer 15..0 a dp 19.16 00000000000 0 c figure 2.6. real mode i387 tm npx instruction and data pointer image in memory, 16-bit format 12
military i387 tm math coprocessor 271074 4 precision control rounding control 00e24 bits (single precision) 00eround to nearest or even 01e(reserved) 01eround down (toward b % ) 10e53 bits (double precision) 10eround up (toward a % ) 11e64 bits (extended precision) 11echop (truncate toward zero) figure 2.7. i387 tm npx control word 2.3.5 control word the npx provides several processing options that are selected by loading a control word from memory into the control register. figure 2.7 shows the format and encoding of fields in the control word. the low-order byte of this control word configures the i387 npx error and exception masking. bits 5 0 of the control word contain individual masks for each of the six exceptions that the i387 processor recog- nizes. the high-order byte of the control word configures the i387 npx operating mode, including precision and rounding. # bit 12 no longer defines infinity control and is a reserved bit. only affine closure is supported for infinity arithmetic. the bit is initialized to zero after reset or finit and is changeable upon loading the cw. programs must ignore this bit. # the rounding control (rc) bits (bits 11 10) pro- vide for directed rounding and true chop, as well as the unbiased round to nearest even mode specified in the ieee standard. rounding control affects only those instructions that perform rounding at the end of the operation (and thus can generate a precision exception); namely, fst, fstp, fist, all arithmetic instructions (ex- cept fprem, fprem1, fxtract, fabs, and fchs), and all transcendental instructions. # the precision control (pc) bits (bits 9 8) can be used to set the i387 npx internal operating preci- sion of the significand at less than the default of 64 bits (extended precision). this can be useful in providing compatibility with early generation arith- metic processors of smaller precision. pc affects only the instructions add, sub, div, mul, and sqrt. for all other instructions, either the preci- sion is determined by the opcode or extended precision is used. 2.4 interrupt description several interrupts of the i386 processor are used to report exceptional conditions while executing nu- meric programs in either real or protected mode. ta- ble 2.6 shows these interrupts and their causes. 13
military i387 tm math coprocessor table 2.6. i386 tm microprocessor interrupt vectors reserved for npx interrupt cause of interrupt number 7 an esc instruction was encountered when em or ts of i386 processor control register zero (cr0) was set. em e 1 indicates that software emulation of the instruction is required. when ts is set, either an esc or wait instruction causes interrupt 7. this indicates that the current npx context may not belong to the current task. 9 an operand of a coprocessor instruction wrapped around an addressing limit (0ffffh for small segments, 0ffffffffh for big segments, zero for expand-down segments) and spanned inaccessible addresses a . the failing numerics instruction is not restartable. the address of the failing numerics instruction and data operand may be lost; an fstenv does not return reliable addresses. as with the m80286/m80287, the segment overrun exception should be handled by executing an fninit instruction (i.e. an finit without a preceding wait). the return address on the stack does not necessarily point to the failing instruction nor to the following instruction. the interrupt can be avoided by never allowing numeric data to start within 108 bytes of the end of a segment. 13 the first word or doubleword of a numeric operand is not entirely within the limit of its segment. the return address pushed onto the stack of the exception handler points at the esc instruction that caused the exception, including any prefixes. the m80387 has not executed this instruction; the instruction pointer and data pointer register refer to a previous, correctly executed instruction. 16 the previous numerics instruction caused an unmasked exception. the address of the faulty instruction and the address of its operand are stored in the instruction pointer and data pointer registers. only esc and wait instructions can cause this interrupt. the m80386 return address pushed onto the stack of the exception handler points to a wait or esc instruction (including prefixes). this instruction can be restarted after clearing the exception condition in the npx. fninit, fnclex, fnstsw, fnstenv, and fnsave cannot cause this interrupt. a. an operand may wrap around an addressing limit when the segment limit is near an addressing limit and the operand is near the largest valid address in the segment. because of the wrap-around, the beginning and ending addresses of such an operand will be at opposite ends of the segment. there are two ways that such an operand may also span inaccessible addresses: 1) if the segment limit is not equal to the addressing limit (e.g. addressing limit is ffffh and segment limit is fffdh) the operand will span addresses that are not within the segment (e.g. an 8-byte operand that starts at valid offset fffc will span addresses fffc ffff and 0000-0003; however addresses fffe and ffff are not valid, because they exceed the limit); 2) if the operand begins and ends in present and accessible pages but intermediate bytes of the operand fall in a not-present page or a page to which the procedure does not have access rights. 2.5 exception handling the i387 npx detects six different exception condi- tions that can occur during instruction execution. ta- ble 2.7 lists the exception conditions in order of precedence, showing for each the cause and the default action taken by the i387 npx if the exception is masked by its corresponding mask bit in the con- trol word. any exception that is not masked by the control word sets the corresponding exception flag of the status word, sets the es bit of the status word, and asserts the error signal. when the cpu attempts to execute another esc instruction or wait, excep- tion 16 occurs. the exception condition must be re- solved via an interrupt service routine. the i386/i387 processor combination saves the address of the floating-point instruction that caused the exception and the address of any memory operand required by that instruction. 2.6 initialization i387 npx initialization software must execute an fninit instruction (i.e. an finit without a preceding wait) to clear error . the fninit is not required for the m80287, though intel documentation recom- mends its use (refer to the numerics supplement to the 80286 programmer's reference manual ). after a hardware reset, the error output is asserted to indicate that an m80387 is present. to accomplish this, the ie and es bits of the status word are set, and the im bit in the control word is reset. after fninit, the status word and the control word have the same values as in an m80287 after reset. 14
military i387 tm math coprocessor 2.7 m8087 and m80287 compatibility this section summarizes the differences between the i387 npx and the m80287. any migration from the m8087 directly to the i387 npx must also take into account the differences between the m8087 and the m80287 as listed in appendix a. many changes have been designed into the i387 npx to directly support the ieee standard in hard- ware. these changes result in increased perform- ance by eliminating the need for software that sup- ports the standard. 2.7.1 general differences the i387 processor supports only affine closure for infinity arithmetic, not projective closure. bit 12 of the control word (cw) no longer defines infinity control. it is a reserved bit; but it is initialized to zero after reset or finit and is changeable upon load- ing the cw. programs must ignore this bit. operands for fscale and fpatan are no longer restricted in range (except for g % ); f2xm1 and fptan accept a wider range of operands. the results of transcendental operations may be slightly different from those computed by m80287. in the case of fptan, the i387 npx supplies a true tangent result in st(1), and (always) a floating point 1inst. rounding control is in effect for fld constant . software cannot change entries of the tag word to values (other than empty) that do not reflect the ac- tual register contents. after reset, finit, and incomplete fprem, the i387 npx resets to zero the condition code bits c 3 c 0 of the status word. in conformance with the ieee standard, the i387 npx does not support the special data formats: pseudozero, pseudo-nan, pseudoinfinity, and un- normal. table 2.7. exceptions exception cause default action (if exception is masked) invalid operation on a signaling nan, unsupported format, result is a quiet nan, integer operation indeterminate form (0 * % , 0/0, ( a % ) a ( b % ), etc.), or indefinite, or bcd indefinite stack overflow/underflow (sf is also set). denormalized at least one of the operands is denormalized, i.e. it has normal processing operand the smallest exponent but a nonzero significand. continues zero divisor the divisor is zero while the dividend is a noninfinite, result is % nonzero number. overflow the result is too large in magnitude to fit in the specified result is largest finite value format. or % underflow the true result is nonzero but too small to be result is denormalized or represented in the specified format, and, if underflow zero exception is masked, denormalization causes loss of accuracy. inexact the true result is not exactly representable in the normal processing result specified format (e.g. 1/3); the result is rounded continues (precision) according to the rounding mode. 15
military i387 tm math coprocessor 2.7.2 exceptions a number of differences exist due to changes in the ieee standard and to functional improvements to the architecture of the m80387: 1. when the overflow or underflow exception is masked, the i387 npx differs from the m80287 in rounding when overflow or underflow occurs. the i387 npx produces results that are consist- ent with the rounding mode. 2. when the underflow exception is masked, the i387 npx sets its underflow flag only if there is also a loss of accuracy during denormalization. 3. fewer invalid-operation exceptions due to de- normal operands, because the instructions fsqrt, fdiv, fprem, and conversions to bcd or to integer normalize denormal operands be- fore proceeding. 4. the fsqrt, fbstp, and fprem instructions may cause underflow, because they support de- normal operands. 5. the denormal exception can occur during the transcendental instructions and the fxtract instruction. 6. the denormal exception no longer takes prece- dence over all other exceptions. 7. when the denormal exception is masked, the i387 npx automatically normalizes denormal op- erands. the m8087/m80287 performs unnormal arithmetic, which might produce an unnormal re- sult. 8. when the operand is zero, the fxtract in- struction reports a zero-divide exception and leaves b % in st(1). 9. the status word has a new bit (sf) that signals when invalid-operation exceptions are due to stack underflow or overflow. 10. fld extended precision no longer reports denor- mal exceptions, because the instruction is not numeric. 11. fld single/double precision when the operand is denormal converts the number to extended precision and signals the denormalized operand exception. when loading a signaling nan, fld single/double precision signals an invalid-oper- and exception. 12. the i387 npx only generates quiet nans (as on the m80287); however, the i387 npx distin- guishes between quiet nans and signaling nans. signaling nans trigger exceptions when they are used as operands; quiet nans do not (except for fcom, fist, and fbstp which also raise ie for quiet nans). 13. when stack overflow occurs during fptan and overflow is masked, both st(0) and st(1) con- tain quiet nans. the m80287/m8087 leaves the original operand in st(1) intact. 14. when the scaling factor is g % , the fscale (st(0), st(1)) instruction behaves as follows (st(0) and st(1) contain the scaled and scaling operands respectively): # fscale(0, % ) generates the invalid operation exception. # fscale(finite, b % ) generates zero with the same sign as the scaled operand. # fscale(finite, a % ) generates % with the same sign as the scaled operand. the m8087/m80287 returns zero in the first case and raises the invalid-operation exception in the other cases. 15. the i387 npx returns signed infinity/zero as the unmasked response to massive overflow/under- flow. the m8087 and m80287 support a limited range for the scaling factor; within this range ei- ther massive overflow/underflow do not occur or undefined results are produced. 3.0 hardware interface 3.1 signal description in the following signal descriptions, the i387 coproc- essor pins are grouped by function as follows: 1. execution controle386clk2, 387clk2, ckm, resetin 2. npx handshakeepereq, busy , error 3. bus interface pinsed31 d0, w/r , ads , ready , readyo 4. chip/port selectesten, nps1 , nps2, cmd0 5. power suppliesev cc ,v ss table 3.1 lists every pin by its identifier, gives a brief description of its function, and lists some of its char- acteristics. all output signals are tristate; they leave floating state only when sten is active. the output buffers of the bidirectional data pins d31 d0 are also tristate; they leave floating state only in read cycles when the i387 npx is selected (i.e. when sten, nps1 , and nps2 are all active). figure 3.1 and table 3.2 together show the location of every pin in the pin grid array. 16
military i387 tm math coprocessor table 3.1. i387 tm npx pin summary pin function active input/ referenced name state output to 386clk2 i386 microprocessor clock 2 i 387clk2 i387 npx clock 2 i ckm i387 npx clocking mode i resetin system reset high i 386clk2 pereq processor extension high o 386clk2/sten request busy busy status low o 386clk2/sten error error status low o 387clk2/sten d31 d0 data pins high i/o 386clk2 w/r write/read bus cycle hi/lo i 386clk2 ads address strobe low i 386clk2 ready bus ready input low i 386clk2 readyo ready output low o 386clk2/sten sten status enable high i 386clk2 nps1 npx select y 1 low i 386clk2 nps2 npx select y 2 high i 386clk2 cmd0 command low i 386clk2 v cc i v ss i note: sten is referenced to only when getting the output pins into or out of tristate mode. table 3.2a. i387 tm npx pga pin cross-reference pin signal a2 d9 a3 d11 a4 d12 a5 d14 a6 v cc a7 d16 a8 d18 a9 v cc a10 d21 b1 d8 b2 v ss b3 d10 b4 v cc b5 d13 b6 d15 b7 v ss b8 d17 pin signal b9 d19 b10 d20 b11 d22 c1 d7 c2 d6 c10 d23 c11 v ss d1 d5 d2 d4 d10 d24 d11 d25 e1 v cc e2 v ss e10 d26 e11 d27 f1 v cc f2 v ss pin signal f10 v cc f11 v ss g1 d3 g2 d2 g10 d28 g11 d29 h1 d1 h2 d0 h10 d30 h11 d31 j1 v ss j2 v cc j10 v ss j11 ckm k1 pereq k2 busy k3 tie high pin signal k4 w/r k5 v cc k6 nps2 k7 ads k8 ready k9 no connect k10 386clk2 k11 387clk2 l2 error l3 readyo l4 sten l5 v ss l6 nps1 l7 v cc l8 cmd0 l9 tie high l10 resetin 17
military i387 tm math coprocessor table 3.2b. i387 tm math coprocessor cqfp pin cross-reference pin signal 1v ss 2v cc 3d4 4d5 5d6 6d7 7d8 8d9 9 d10 10 d11 11 d12 12 v ss 13 v cc 14 d13 15 d14 16 v ss 17 v cc pin signal 18 d15 19 v ss 20 v cc 21 v ss 22 d16 23 d17 24 d18 25 d19 26 d20 27 d21 28 d22 29 d23 30 d24 31 d25 32 v cc 33 d26 34 d27 pin signal 35 v ss 36 v cc 37 d28 38 d29 39 v cc 40 d30 41 d31 42 ckm 43 386clk2 44 387clk2 45 resetin 46 nc 47 tie high 48 ready 49 v ss 50 cmd0 51 ads pin signal 52 v cc 53 v ss 54 nps2 55 nps1 56 v ss 57 w/r 58 sten 59 tie high 60 readyo 61 busy 62 error 63 pereq 64 d0 65 d1 66 d2 67 d3 68 v cc 18
military i387 tm math coprocessor 271074 5 i387 math coprocessor pga pinouteview from pin side 271074 20 i387 math coprocessor pga pinouteview from top side 271074 19 mq80387 68-lead quad flat pack top view figure 3.1. i387 tm npx pin configuration 19
military i387 tm math coprocessor 3.1.1 m80386 clock 2 (386clk2) this input uses the m80386 clk2 signal to time the bus control logic. several other m80387 signals are referenced to the rising edge of this signal. when ckm e 1 (synchronous mode) this pin also clocks the data interface and control unit and the floating- point unit of the m80387. this pin requires mos-lev- el input. the signal on this pin is divided by two to produce the internal clock signal clk. 3.1.2 m80387 clock 2 (387clk2) when ckm e 0 (asynchronous mode) this pin pro- vides the clock for the data interface and control unit and the floating-point unit of the m80387. in this case, the ratio of the frequency of 387clk2 to the frequency of 386clk2 must lie within the range 10:16 to 14:10. when ckm e 1 (synchronous mode) this pin is ignored; 386clk2 is used instead for the data interface and control unit and the float- ing-point unit. this pin requires ttl-level input. 3.1.3 m80387 clocking mode (ckm) this pin is a strapping option. when it is strapped to v cc , the i387 npx operates in synchronous mode; when strapped to v ss , the i387 npx operates in asynchronous mode. these modes relate to clock- ing of the data interface and control unit and the floating-point unit only; the bus control logic always operates synchronously with respect to the i386 processor. 3.1.4 system reset (resetin) a low to high transition on this pin causes the i387 npx to terminate its present activity and to en- ter a dormant state. resetin must remain high for at least 40 387clk2 periods. the high to low transitions of resetin must be synchronous with 386clk2, so that the phase of the internal clock of the bus control logic (which is the 386clk2 divided by 2) is the same as the phase of the internal clock of the i386 microprocessor. after resetin goes low, at least 50 387clk2 periods must pass before the first npx instruction is written into the i387 co- processor. this pin should be connected to the i386 microprocessor reset pin. table 3.3 shows the status of other pins after a reset. table 3.3. output pin status during reset pin value pin name high readyo , busy low pereq, error tri-state off d31 d0 3.1.5 processor extension request (pereq) when active, this pin signals to the i386 cpu that the i387 npx is ready for data transfer to/from its data fifo. when all data is written to or read from the data fifo, pereq is deactivated. this signal always goes inactive before busy goes inactive. this signal is referenced to 386clk2. it should be connected to the i386 microprocessor pereq input. refer to figure 3.7 for the timing relationships be- tween this and the busy and error pins. 3.1.6 busy status (busy ) when active, this pin signals to the i386 cpu that the i387 npx is currently executing an instruction. this signal is referenced to 386clk2. it should be connected to the i386 microprocessor busy pin. refer to figure 3.7 for the timing relationships be- tween this and the pereq and error pins. 3.1.7 error status (error ) this pin reflects the es bits of the status register. when active, it indicates that an unmasked excep- tion has occurred (except that, immediately after a reset, it indicates to the i386 microprocessor that an i387 npx is present in the system). this signal can be changed to inactive state only by the following instructions (without a preceding wait): fninit, fnclex, fnstenv, and fnsave. this signal is referenced to 387clk2. it should be connected to the i386 microprocessor error pin. refer to fig- ure 3.7 for the timing relationships between this and the pereq and busy pins. 20
military i387 tm math coprocessor 3.1.8 data pins (d31 d0) these bidirectional pins are used to transfer data and opcodes between the i386 microprocessor and i387 npx. they are normally connected directly to the corresponding i386 processor data pins. high state indicates a value of one. d0 is the least signifi- cant data bit. timings are referenced to 386clk2. 3.1.9 write/read bus cycle (w/r ) this signal indicates to the i387 npx whether the i386 processor bus cycle in progress is a read or a write cycle. this pin should be connected directly to the i386 processor w/r pin. high indicates a write cycle; low, a read cycle. this input is ignored if any of the signals sten, nps1 , or nps2 is inactive. set- up and hold times are referenced to 386clk2. 3.1.10 address strobe (ads ) this input, in conjunction with the ready input indi- cates when the i387 npx bus-control logic may sample w/r and the chip-select signals. setup and hold times are referenced to 386clk2. this pin should be connected to the i386 processor ads pin. 3.1.11 bus ready input (ready ) this input indicates to the i387 npx when an i386 processor bus cycle is to be terminated. it is used by the bus-control logic to trace bus activities. bus cy- cles can be extended indefinitely until terminated by ready . this input should be connected to the same signal that drives the i386 processor read input. setup and hold times are referenced to 386clk2. 3.1.12 ready output (readyo ) this pin is activated at such a time that write cycles are terminated after two clocks and read cycles after three clocks. in configurations where no extra wait states are required, it can be used to directly drive the i386 processor ready input. refer to section 3.4 ``bus operation'' for details. this pin is activated only during bus cycles that select the i387 npx. this signal is referenced to 386clk2. 3.1.13 status enable (sten) this pin serves as a chip select for the i387 npx. when inactive, this pin forces busy , pereq, error , and readyo outputs into floating state. d31 d0 are normally floating and leave floating state only if sten is active and additional conditions are met. sten also causes the chip to recognize its other chip-select inputs. sten makes it easier to do on-board testing (using the overdrive method) of other chips in systems containing the i387 npx. sten should be pulled up with a resistor so that it can be pulled down when testing. in boards that do not use on-board testing, sten should be connect- ed to v cc . setup and hold times are relative to 386clk2. note that sten must maintain the same setup and hold times as nps1 , nps2, and cmd0 (i.e. if sten changes state during an m80387 bus cycle, it should change state during the same clk period as the nps1 , nps2, and cmd0 signals). 3.1.14 npx select y 1 (nps1 ) when active (along with sten and nps2) in the first period of an i386 microprocessor bus cycle, this sig- nal indicates that the purpose of the bus cycle is to communicate with the i387 npx. this pin should be connected directly to the i386 processor m/io pin, so that the i387 npx is selected only when the m80386 performs i/o cycles. setup and hold times are referenced to 386clk2. 3.1.15 npx select y 2 (nps2) when active (along with sten and nps1 ) in the first period of an i386 processor bus cycle, this signal indicates that the purpose of the bus cycle is to com- municate with the i387 npx. this pin should be con- nected directly to the i386 microprocessor a31 pin, so that the i387 npx is selected only when the i386 processor uses one of the i/o addresses reserved for the i387 npx (800000f8 or 800000fc). setup and hold times are referenced to 386clk2. 3.1.16 command (cmd0 ) during a write cycle, this signal indicates whether an opcode (cmd0 active) or data (cmd0 inactive) is being sent to the i387 npx. during a read cycle, it indicates whether the control or status register (cmd0 active) or a data register (cmd0 inactive) is being read. cmd0 should be connected directly to the a2 output of the i386 microprocessor. setup and hold times are referenced to 386clk2. 3.2 processor architecture as shown by the block diagram on the front page, the npx is internally divided into three sections: the bus control logic (bcl), the data interface and con- trol unit, and the floating point unit (fpu). the fpu (with the support of the control unit which contains the sequencer and other support units) executes all numerics instructions. the data interface and control unit is responsible for the data flow to and from the fpu and the control registers, for receiving the in- 21
military i387 tm math coprocessor structions, decoding them, and sequencing the mi- croinstructions, and for handling some of the admin- istrative instructions. the bcl is responsible for i386 processor bus tracking and interface. the bcl is the only unit in the i387 npx that must run synchronous- ly with the i386 processor; the rest of the i387 npx can run asynchronously with respect to the i386 processor. 3.2.1 bus control logic the bcl communicates solely with the cpu using i/o bus cycles. the bcl appears to the cpu as a special peripheral device. it is special in two re- spects: the cpu initiates i/o automatically when it encounters esc instructions, and the cpu uses re- served i/o addresses to communicate with the bcl. the bcl does not communicate directly with memo- ry. the cpu performs all memory access, transfer- ring input operands from memory to the i387 npx and transferring outputs from the i387 npx to mem- ory. 3.2.2 data interface and control unit the data interface and control unit latches the data and, subject to bcl control, directs the data to the fifo or the instruction decoder. the instruction de- coder decodes the esc instructions sent to it by the cpu and generates controls that direct the data flow in the fifo. it also triggers the microinstruction se- quencer that controls execution of each instruction. if the esc instruction is finit, fclex, fstsw, fstsw ax, or fstcw, the control executes it inde- pendently of the fpu and the sequencer. the data interface and control unit is the one that generates the busy , pereq and error signals that syn- chronize i387 npx activities with the i386 processor. it also supports the fpu in all operations that it can- not perform alone (e.g. exceptions handling, tran- scendental operations, etc.). 3.2.3 floating point unit the fpu executes all instructions that involve the register stack, including arithmetic, logical, transcen- dental, constant, and data transfer instructions. the data path in the fpu is 84 bits wide (68 significant bits, 15 exponent bits, and a sign bit) which allows internal operand transfers to be performed at very high speeds. 3.3 system configuration as an extension to the i386 processor, the i387 npx can be connected to the cpu as shown by figure 3.2. a dedicated communication protocol makes 271074 6 figure 3.2. i386 tm /i387 tm processors system configuration 22
military i387 tm math coprocessor table 3.4. bus cycles definition sten nps1 nps2 cmd0 w/r bus cycle type 0 x x x x i387 npx not selected and all outputs in floating state 1 1 x x x i387 npx not selected 1 x 0 x x i387 npx not selected 1 0 1 0 0 cw or sw read from i387 npx 1 0 1 0 1 opcode write to i387 npx 1 0 1 1 0 data read from i387 npx 1 0 1 1 1 data write to i387 npx possible high-speed transfer of opcodes and oper- ands between the i386 microprocessor and i387 npx. the i387 npx is designed so that no additional components are required for interface with the i386 processor. the i387 npx shares the 32-bit wide lo- cal bus of the i386 processor and most control pins of the i387 npx are connected directly to pins of the i386 processor. 3.3.1 bus cycle tracking the ads and ready signals allow the i387 npx to track the beginning and end of i386 processor bus cycles, respectively. when ads is asserted at the same time as the i387 npx chip-select inputs, the bus cycle is intended for the i387 npx. to signal the end of a bus cycle for the i387 npx, ready may be asserted directly or indirectly by the i387 npx or by other bus-control logic. refer to table 3.4 for defini- tion of the types of i387 npx bus cycles. 3.3.2 i387 tm npx addressing the nps1 , nps2 and sten signals allow the npx to identify which bus cycles are intended for the npx. the npx responds only to i/o cycles when bit 31 of the i/o address is set. in other words, the npx acts as an i/o device in a reserved i/o address space. because a 31 is used to select the i387 npx for data transfers, it is not possible for a program running on the i386 processor to address the i387 npx with an i/o instruction. only esc instructions cause the i386 processor to communicate with the i387 npx. the i386 processor bs16 input must be inactive dur- ing i/o cycles when a 31 is active. 3.3.3 function selection the cmd0 and w/r signals identify the four kinds of bus cycle: control or status register read, data read, opcode write, data write. 3.3.4 cpu/npx synchronization the pin pairs busy , pereq, and error are used for various aspects of synchronization between the cpu and the npx. busy is used to synchronize instruction transfer from the i386 processor to the i387 npx. when the i387 npx recognizes an esc instruction, it asserts busy . for most esc instructions, the i386 proces- sor waits for the i387 npx to deassert busy before sending the new opcode. the npx uses the pereq pin of the i386 cpu to signal that the npx is ready for data transfer to or from its data fifo. the npx does not directly ac- cess memory; rather, the i386 processor provides memory access services for the npx. thus, memory access on behalf of the npx always obeys the rules applicable to the mode of the i386 processor, wheth- er the i386 processor be in real-address mode or protected mode. once the i386 processor initiates an i387 npx in- struction that has operands, the i386 microproces- sor waits for pereq signals that indicate when the i387 npx is ready for operand transfer. once all op- erands have been transferred (or if the instruction has no operands) the i386 microprocessor contin- ues program execution while the i387 npx executes the esc instruction. in m8086/m8087 systems, wait instructions may be required to achieve synchronization of both com- mands and operands. in m80286/m80287 and i386/i387 processor systems, wait instructions are required only for operand synchronization; namely, after npx stores to memory (except fstsw and fstcw) or loads from memory. used this way, wait ensures that the value has already been writ- ten or read by the npx before the cpu reads or changes the value. once it has started to execute a numerics instruction and has transferred the operands from the i386 23
military i387 tm math coprocessor processor, the i387 npx can process the instruction in parallel with and independent of the host cpu. when the npx detects an exception, it asserts the error signal, which causes an i386 processor in- terrupt. 3.3.5 synchronous or asynchronous modes the internal logic of the i387 npx (the fpu) can either operate directly from the cpu clock (synchro- nous mode) or from a separate clock (asynchronous mode). the two configurations are distinguished by the ckm pin. in either case, the bus control logic (bcl) of the i387 npx is synchronized with the cpu clock. use of asynchronous mode allows the i386 microprocessor and the fpu section of the i387 npx to run at different speeds. in this case, the ratio of the frequency of 387clk2 to the frequency of 386clk2 must lie within the range 10:16 to 16:10. use of synchronous mode eliminates one clock gen- erator from the board design. 3.3.6 automatic bus cycle termination in configurations where no extra wait states are re- quired, readyo can be used to drive the i386 mi- croprocessor ready input. if this pin is used, it should be connected to the logic that ors all ready outputs from peripherals on the i386 micro- processor bus. readyo is asserted by the i387 npx only during i/o cycles that select the i387 npx. refer to section 3.4 ``bus operation'' for details. 3.4 bus operation with respect to the bus interface, the i387 npx is fully synchronous with the i386 processor. both op- erate at the same rate, because each generates its internal clk signal by dividing 386clk2 by two. the i386 processor initiates a new bus cycle by acti- vating ads . the i387 npx recognizes a bus cycle, if, during the cycle in which ads is activated, sten, nps1 , and nps2 are all activated. proper operation is achieved if nps1 is connected to the m/io output of the i386 processor, and nps2 to the a31 output. the i386 processor's a31 output is guaranteed to be inactive in all bus cycles that do not address the i387 npx (i.e. i/o cycles to other devices, interrupt ac- knowledge, and reserved types of bus cycles). sys- tem logic must not signal a 16-bit bus cycle via the i386 processor bs16 input during i/o cycles when a31 is active. during the clk period in which ads is activated, the i387 npx also examines the w/r input signal to de- termine whether the cycle is a read or a write cycle and examines the cmd0 input to determine whether an opcode, operand, or control/status reg- ister transfer is to occur. the i387 npx supports both pipelined and nonpipe- lined bus cycles. a nonpipelined cycle is one for which the i386 processor asserts ads when no oth- er i387 npx bus cycle is in progress. a pipelined bus cycle is one for which the i386 processor asserts ads and provides valid next-address and control signals as soon as in the second clk period after the ads assertion for the previous i386 processor bus cycle. pipelining increases the availability of the bus by at least one clk period. the i387 npx sup- ports pipelined bus cycles in order to optimize ad- dress pipelining by the i386 processor for memory cycles. bus operation is described in terms of an abstract state machine . figure 3.3 illustrates the states and state transitions for i387 npx bus cycles: # t i is the idle state. this is the state of the bus logic after reset, the state to which bus logic returns after evey nonpipelined bus cycle, and the state to which bus logic returns after a series of pipelined cycles. # t rs is the ready sensitive state. different types of bus cycle may require a minimum of one or two successive t rs states. the bus logic remains in t rs state until ready is sensed, at which point the bus cycle terminates. any number of wait states may be implemented by delaying ready , thereby causing additional successive t rs states. # t p is the first state for every pipelined bus cycle. the readyo output of the i387 npx indicates when a bus cycle for the i387 npx may be terminat- ed if no extra wait states are required. for all write cycles (except those for the instructions fldenv and frstor), readyo is always assert- 271074 7 figure 3.3. bus state diagram 24
military i387 tm math coprocessor ed in the first t rs state, regardless of the number of wait states. for all read cycles and write cycles for fldenv and frstor, readyo is always asserted in the second t rs state, regardless of the number of wait states. these rules apply to both pipelined and nonpipelined cycles. systems designers may use readyo in one of three ways: 1. leave it disconnected and use external logic to generate ready signals. when choosing this op- tion, i387 npx requirements for wait states in read cycles and write cycles of fldenv and frstor must be obeyed. 2. connect it (directly or through logic that ors ready signals from other devices) to the ready inputs of the i386 processor and i387 npx. 3. use it as one input to a wait-state generator. the following sections illustrate different types of i387 npx bus cycles. because different instructions have different amounts of overhead before, between, and after op- erand transfer cycles, it is not possible to represent in a few diagrams all of the combinations of succes- sive operand transfer cycles. the following bus-cy- cle diagrams show memory cycles between i387 npx operand-transfer cycles. note however that, during the instructions fldenv, fstenv, fsave, and frstor, some consecutive accesses to the npx do not have intervening memory accesses. for the timing relationship between operand transfer cy- cles and opcode write or other overhead activities, see figure 3.7. 3.4.1 nonpipelined bus cycles figure 3.4 illustrates bus activity for consecutive nonpipelined bus cycles. 3.4.1.1 write cycle at the second clock of the bus cycle, the m80387 enters the t rs (ready -sensitive) state. during this state, the i387 npx samples the ready input and stays in this state as long as ready is inactive. in write cycles, the i387 npx drives the readyo signal for one clk period beginning with the second clk of the bus cycle; therefore, the fastest write cycle takes two clk cycles (see cycle 2 of figure 3.4). for the instructions fldenv and frstor, however, the i387 npx forces a wait state by delay- ing the activation of readyo to the second t rs cycle (not shown in figure 3.4). when ready is asserted the m80387 returns to the idle state, in which ads could be asserted again by the i386 processor for the next cycle. 3.4.1.2 read cycle at the second clock of the bus cycle, the i387 npx enters the t rs state. see figure 3.4. in this state, the i387 npx samples the ready input and stays in this state as long as ready is inactive. at the rising edge of clk in the second clock period of the cycle, the i387 npx starts to drive the d31 d0 outputs and continues to drive them as long as it stays in t rs state. in read cycles that address the i387 npx, at least one wait state must be inserted to insure that the i386 microprocessor latches the correct data. since the i387 npx starts driving the system data bus only at the rising edge of clk in the second clock period of the bus cycle, not enough time is left for the data signals to propagate and be latched by the i386 processor at the falling edge of the same clock peri- od. the i387 npx drives the readyo signal for one clk period in the third clk of the bus cycle. there- fore, if the readyo output is used to drive the i386 processor ready input, one wait state is inserted automatically. because one wait state is required for i387 npx reads, the minimum is three clk cycles per read, as cycle 3 of figure 3.4 shows. when ready is asserted the i387 npx returns to the idle state, in which ads could be asserted again by the i386 processor for the next cycle. the tran- sition from t rs state to idle state causes the i387 npx to put the tristate d31 d0 outputs into the floating state, allowing another device to drive the system data bus. 25
military i387 tm math coprocessor 271074 8 cycle s1&2 represent part of the operand transfer cycle for instructions involving either 4-byte or 8-byte operand loads. cycle s3&4 represent part of the operand transfer cycle for a store operation. * cycle s1&2 could repeat here or t i states for various non-operand transfer cycles and overhead. figure 3.4. nonpipelined read and write cycles 3.4.2 pipelined bus cycles because all the activities of the i387 npx bus inter- face occur either during the t rs state or during the transitions to or from that state, the only difference between a pipelined and a nonpipelined cycle is the manner of changing from one state to another. the exact activities in each state are detailed in the pre- vious section ``nonpipelined bus cycles''. when the i386 processor asserts ads before the end of a bus cycle, both ads and ready are active during a t rs state. this condition causes the i387 npx to change to a different state named t p . the i387 npx activities in the transition from a t rs state to a t p state are exactly the same as those in the transition from a t rs state to a t i state in non- pipelined cycles. t p state is metastable; therefore, one clock period later the i387 npx returns to t rs state. in consecutive pipelined cycles, the i387 npx bus logic uses only t rs and t p states. figure 3.5 shows the fastest transition into and out of the pipelined bus cycles. cycle 1 in this figure represents a nonpipelined cycle. (nonpipelined write cycles with only one t rs state (i.e. no wait states) are always followed by another nonpipelined cycle, because ready is asserted before the earliest pos- sible assertion of ads for the next cycle.) figure 3.6 shows the pipelined write and read cycles with one additional t rs states beyond the minimum required. to delay the assertion of ready requires external logic. 26
military i387 tm math coprocessor 3.4.3 bus cycles of mixed type when the i387 npx bus logic is in the t rs state, it distinguishes between nonpipelined and pipelined cycles according to the behavior of ads and ready . in a nonpipelined cycle, only ready is acti- vated, and the transition is from t rs to idle state. in a pipelined cycle, both ready and ads are active and the transition is first from t rs state to t p state then, after one clock period, back to t rs state. 3.4.4 busy and pereq timing relationship figure 3.7 shows the activation of busy at the be- ginning of instruction execution and its deactivation after execution of the instruction is complete. per- eq is activated in this interval. if error (not shown in the diagram) is ever asserted, it would occur at least six 386clk2 periods after the deactivation of pereq and at least six 386clk2 periods before the deactivation of busy . figure 3.7 shows also that sten is activated at the beginning of a bus cycle. 271074 9 cycle 1 cycle 4 represent the operand transfer cycle for an instruction involving a transfer of two 32-bit loads in total. the opcode write cycles and other overhead are not shown. note that the next cycle will be a pipelined cycle if both ready and ads are sampled active at the end of a t rs state of the current cycle. figure 3.5. fastest transitions to and from pipelined cycles 27
military i387 tm math coprocessor 271074 10 note: 1. cycles between operand write to the npx and storing result. figure 3.6. pipelined cycles with wait states 271074 11 notes: 1. instruction dependent. 2. pereq is an asynchronous input to the i386 processor; it may not be asserted (instruction dependent). 3. more operand transfers. 4. memory read (operand) cycle is not shown. figure 3.7. sten, busy and pereq timing relationship 28
military i387 tm math coprocessor 5.0 electrical data 5.1 absolute maximum ratings * case temperature under bias b 55 cto a 125 c storage temperature b 65 cto a 150 c voltage on any pin with respect to ground b 0.5 to v cc a 0.5v power dissipation1.5w notice: this is a production data sheet. the specifi- cations are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. operating conditions mil-std-883 table 5.1 symbol description min max units t c case temperature (instant on) b 55 a 125 c v cc digital supply voltage 4.75 5.25 v extended temperature symbol description min max units t c case temperature (instant on) b 40 a 110 c v cc digital supply voltage 4.75 5.25 v military temperature only (mto) symbol description min max units t c case temperature (instant on) b 55 a 125 c v cc digital supply voltage 4.75 5.25 v 29
military i387 tm math coprocessor 5.2 dc characteristics (over specified operating conditions) table 5.2. dc specifications symbol parameter min max units comments v il input lo voltage b 0.3 a 0.8 v (note 1) v ih input hi voltage 2.0 v cc a 0.3 v (note 1) v cl 386clk2 input lo voltage b 0.3 a 0.8 v v ch 386clk2 input hi voltage 3.7 v cc a 0.3 v v ol output lo voltage 0.45 v (note 2) v oh output hi voltage 2.4 v (note 3) i cc power supply current 150 (typical) 250 ma 387clk2 e 32 mhz (4) 190 (typical) 310 387clk2 e 40 mhz (4) 250 (typical) 390 387clk2 e 50 mhz (4) i li input leakage current g 15 m a0v s v in s v cc i lo i/o leakage current g 15 m a 0.45v s v o s v cc c in input capacitance 10 pf fc e 1 mhz c o i/o or output capacitance 12 pf fc e 1 mhz c clk clock capacitance 20 pf fc e 1 mhz notes: 1. this parameter is for all inputs, including 387clk2 but excluding 386clk2. 2. this parameter is measured at i ol as follows: data e 4.0 ma readyo e 2.5 ma error , busy , pereq e 2.5 ma 3. this parameter is measured at i oh as follows: data e 1.0 ma readyo e 0.6 ma error , busy , pereq e 0.6 ma 4. i cc is measured at steady state, maximum capacitive loading on the outputs, and worst-case dc level at the inputs; 386clk2 at the same frequency as 387clk2. 30
military i387 tm math coprocessor 5.3 ac characteristics (over specified operating conditions) output trip level: 1.5v table 5.3a. combinations of bus interface and execution speeds speed combinations functional block i387-16 i387-20 i387-25 bus interface unit (mhz) 16 20 25 execution unit (mhz) 16 20 25 table 5.3b. timing requirements of the execution unit pin symbol parameter 16 mhz 20 mhz 25 mhz comments 1.5v 1.5v 1.5v min max min max min max (ns) (ns) (ns) (ns) (ns) (ns) 387clk2 t1 period 31 125 25 125 20 125 2.0v 387clk2 t2a high time 9 8 7 2.0v 387clk2 t2b high time 5 5 4 3.7v 387clk2 t3a low time 9 8 7 2.0v 387clk2 t3b low time 7 6 5 0.8v 387clk2 t4 fall time 8 8 7 3.7v to 0.8v 387clk2 t5 rise time 8 8 7 0.8v to 3.7v table 5.3c. timing requirements of the bus interface unit pin symbol parameter 16 mhz 20 mhz 25 mhz comments 1.5v 1.5v 1.5v min max min max min max (ns) (ns) (ns) (ns) (ns) (ns) 386clk2 t1 period 31 125 25 125 20 125 2.0v 386clk2 t2a high time 9 8 7 2.0v 386clk2 t2b high time 5 5 4 3.7v 386clk2 t3a low time 9 8 7 2.0v 386clk2 t3b low time 7 6 5 0.8v 386clk2 t4 fall time 8 8 7 3.7v to 0.8v 386clk2 t5 rise time 8 8 7 0.8v to 3.7v 386clk2/ ratio 10/16 14/10 10/16 14/10 10/16 14/10 387clk2 readyo t7 out delay 4 34 3 31 3 24 c l e 75 pf * readyo t7 out delay 4 31 3 27 3 21 c l e 25 pf pereq t7 out delay 5 34 5 34 4 33 c l e 75 pf * busy t7 out delay 5 34 5 29 4 29 c l e 75 pf * busy t7 out delay n/a n/a n/a n/a 4 27 c l e 25 pf error t7 out delay 5 34 5 34 4 33 c l e 75 pf * * c l e 50 pf for 25 mhz timing. note: 1. float conditions occurs when maximum output current becomes less than i lo in magnitude. 31
military i387 tm math coprocessor table 5.3d. timing requirements of the bus interface unit (continued) pin symbol parameter 16 mhz 20 mhz 25 mhz comments 1.5v 1.5v 1.5v min max min max min max (ns) (ns) (ns) (ns) (ns) (ns) d31 d0 t8 out delay 1 54 1 54 0 50 c l e 120 pf * d31 d0 t10 setup time 11 11 11 d31 d0 t11 hold time 11 11 11 d31 d0 t12 (note 1) float time 6 33 6 27 5 24 c l e 120 pf * pereq t13 (note 1) float time 1 60 1 50 1 40 c l e 75 pf * busy t13 (note 1) float time 1 60 1 50 1 40 c l e 75 pf * error t13 (note 1) float time 1 60 1 50 1 40 c l e 75 pf * readyo t13 (note 1) float time 1 60 1 50 1 40 c l e 75 pf * ads t14 setup time 26 21 16 ads t15 hold time 5 5 4 w/r t14 setup time 26 21 16 w/r t15 hold time 5 5 4 ready t16 setup time 21 12 9 ready t17 hold time 4 4 4 cmd0 t16 setup time 21 19 16 cmd0 t17 hold time 2 4 4 nps1 t16 setup time 21 19 16 nps2 nps1 t17 hold time 2 2 4 nps2 sten t16 setup time 21 21 15 sten t17 hold time 2 2 2 resetin t18 setup time 13 12 10 resetin t19 hold time 4 4 3 * c l e 50 pf for 25 mhz timing. note: 1. float conditions occurs when maximum output current becomes less than i lo in magnitude. float delay is not tested. 32
military i387 tm math coprocessor 271074 13 figure 5.1. 386clk2/387clk2 waveform and measurement points for input/output ac specifications 271074 14 figure 5.2. output signals 33
military i387 tm math coprocessor 271074 15 figure 5.3. input and i/o signals note: 271074 16 the second internal processor phase following reset high to low transition is ph2. figure 5.4. reset signal 271074 17 figure 5.5. float from sten 34
military i387 tm math coprocessor table 5.4. other parameters pin symbol parameter min max units resetin t30 duration 40 387clk2 resetin t31 resetin inactive to 1st opcode write 50 387clk2 busy t32 duration 6 386clk2 busy , error t33 error (in) active to busy inactive 6 386clk2 pereq, error t34 pereq inactive to error active 6 386clk2 ready , busy t35 ready active to busy active 4 4 386clk2 ready t36 minimum time from opcode write to 6 386clk2 opcode/operand write ready t37 minimum time from operand write to 8 386clk2 operand write 271074 18 * in 387clk2's ** or last operand note: 1. memory read (operand) cycle is not shown. figure 5.6. other parameters 35
military i387 tm math coprocessor instruction optional first byte second byte fields 1 11011 opa 1 mod 1 opb r/m sib disp 2 11011 mf opa mod opb r/m sib disp 3 11011 d p opa 1 1 opb st(i) 4 11011 0 0 1 1 1 1 op 5 11011 0 1 1 1 1 1 op 1511 10 9 8 7 6 5 43210 6.0 i387 tm numerics coprocessor extensions to the i386 tm microprocessor instruction set instructions for the i387 npx assume one of the five forms shown in the following table. in all cases, in- structions are at least two bytes long and begin with the bit pattern 11011b, which identifies the escape class of instruction. instructions that refer to memory operands specify addresses using the i386 proces- sor addressing modes. op e instruction opcode, possible split into two fields opa and opb mf e memory format 00e32-bit real 01e32-bit integer 10e64-bit real 11e16-bit integer p e pop 0edo not pop stack 1epop stack after operation esc e 11011 d e destination 0edestination is st(0) 1edestination is st(i) r xor d e 0edestination (op) source r xor d e 1esource (op) destination st(i) e register stack element i 000 e stack top 001 e second stack element # # # 111 e eighth stack element mod (mode field) and r/m (register/memory spec- ifier) have the same interpretation as the corre- sponding fields of i386 processor instructions (refer to i386 microprocessor programmer's reference manual ) sib (scale index base) byte and disp (displace- ment) are optionally present in instructions that have mod and r/m fields. their presence depends on the values of mod and r/m, as for i386 processor instructions. the instruction summaries that follow assume that the instruction has been prefetched, decoded, and is ready for execution; that bus cycles do not require wait states; that there are no local bus hold re- quest delaying processor access to the bus; and that no exceptions are detected during instruction execution. if the instruction has mod and r/m fields that call for both base and index registers, add one clock. 36
military i387 tm math coprocessor i387 tm npx extensions to the i386 processor instruction set encoding clock count range instruction byte byte optional 32-bit 32-bit 64-bit 16-bit 0 1 bytes 2 6 real integer real integer data transfer fld e load a integer/real memory to st(0) esc mf 1 mod 000 r/m sib/disp 20 45 52 25 61 65 long integer memory to st(0) esc 111 mod 101 r/m sib/disp 56 67 extended real memory to st(0) esc 011 mod 101 r/m sib/disp 44 bcd memory to st(0) esc 111 mod 100 r/m sib/disp 266 275 st(i) to st(0) esc 001 11000 st(i) 14 fst e store st(0) to integer/real memory esc mf 1 mod 010 r/m sib/disp 44 79 93 45 82 95 st(0) to st(i) esc 101 11010 st(i) 11 fstp e store and pop st(0) to integer/real memory esc mf 1 mod 011 r/m sib/disp 44 79 93 45 82 95 st(0) to long integer memory esc 111 mod 111 r/m sib/disp 80 97 st(0) to extended real esc 011 mod 111 r/m sib/disp 53 st(0) to bcd memory esc 111 mod 110 r/m sib/disp 512 534 st(0) to st(i) esc 101 11001 st (i) 12 fxch e exchange st(i) and st(0) esc 001 11001 st(i) 18 comparison fcom e compare integer/real memory to st(0) esc mf 0 mod 010 r/m sib/disp 26 56 63 31 71 75 st(i) to st(0) esc 000 11010 st(i) 24 fcomp e compare and pop integer/real memory to st esc mf 0 mod 011 r/m sib/disp 26 56 63 31 71 75 st(i) to st(0) esc 000 11011 st(i) 26 fcompp e compare and pop twice st(1) to st(0) esc 110 1101 1001 26 ftst e test st(0) esc 001 1110 0100 28 fucom e unordered compare esc 101 11100 st(i) 24 fucomp e unordered compare and pop esc 101 11101 st(i) 26 fucompp e unordered compare and pop twice esc 010 1110 1001 26 fxam e examine st(0) esc 001 11100101 30-38 constants fldz e load a 0.0 into st(0) esc 001 1110 1110 20 fld1 e load a 1.0 into st(0) esc 001 1110 1000 24 fldpi e load pi into st(0) esc 001 1110 1011 40 fldl2t e load log 2 (10) into st(0) esc 001 1110 1001 40 shaded areas indicate instructions not available in m8087/m80287. note: a. when loading single- or double-precision zero from memory, add 5 clocks. 37
military i387 tm math coprocessor i387 tm npx extensions to the i386 tm processor instruction set (continued) encoding clock count range instruction byte byte optional 32-bit 32-bit 64-bit 16-bit 0 1 bytes 2 6 real integer real integer constants (continued) fldl2e e load log 2 (e) into st(0) esc 001 1110 1010 40 fldlg2 e load log 10 (2) into st(0) esc 001 1110 1100 41 fldln2 e load log e (2) into st(0) esc 001 1110 1101 41 arithmetic fadd e add integer/real memory with st(0) esc mf 0 mod 000 r/m sib/disp 24 32 57 72 29 37 71 85 st(i) and st(0) es cdp0 11000 st(i) 23 31 b fsub e subtract integer/real memory with st(0) esc mf 0 mod 10 r r/m sib/disp 24 32 57 82 28 36 71 83 c st(i) and st(0) es cdp0 1110 r r/m 26 34 d fmul e multiply integer/real memory with st(0) esc mf 0 mod 001 r/m sib/disp 27 35 61 82 32 57 76 87 st(i) and st(0) es cdp0 1100 1 r/m 29 57 e fdiv e divide integer/real memory with st(0) esc mf 0 mod 11 r r/m sib/disp 89 120 127 f 94 136 140 g st(i) and st(0) es cdp0 1111 r r/m 88 h fsqrt i e square root esc 001 1111 1010 122 129 fscale e scale st(0) by st(1) esc 001 1111 1101 67 86 fprem e partial remainder esc 001 1111 1000 74 155 fprem1 e partial remainder (ieee) esc 001 1111 0101 95 185 frndint e round st(0) esc 001 1111 1100 66 80 to integer fxtract e extract components of st(0) esc 001 1111 0100 70 76 fabs e absolute value of st(0) esc 001 1110 0001 22 fchs e change sign of st(0) esc 001 1110 0000 24 25 shaded areas indicate instructions not available in m8087/m80287. notes: b. add 3 clocks to the range when d e 1. c. add 1 clock to each range when r e 1. d. add 3 clocks to the range when d e 0. e. typical e 52 (when d e 0, 46 54, typical e 49). f. add 1 clock to the range when r e 1. g. 135 141 when r e 1. h. add 3 clocks to the range when d e 1. i. b 0 s st(0) s a % . 38
military i387 tm math coprocessor i387 tm npx extensions to the i386 tm processor instruction set (continued) encoding instruction byte byte optional clock count range 0 1 bytes 2 6 transcendental fcos k e cosine of st(0) esc 001 1111 1111 123 772 j fptan k e partial tangent of st(0) esc 001 1111 0010 191 497 j fpatan e partial arctangent esc 001 1111 0011 314 487 fsin k e sine of st(0) esc 001 1111 1110 122 771 j fsincos k e sine and cosine of st(0) esc 001 1111 1011 194 809 j f2xm1 l e 2 st(0) b 1 esc 001 1111 0000 211 476 fyl2x m e st(1) * log 2 (st(0)) esc 001 1111 0001 120 538 fyl2xp1 n e st(1) * log 2 (st(0) a 1.0) esc 001 1111 1001 257 547 processor control finit e initialize npx esc 011 1110 0011 33 fstsw ax e store status word esc 111 1110 0000 13 fldcw e load control word esc 001 mod 101 r/m sib/disp 19 fstcw e store control word esc 101 mod 111 r/m sib/disp 15 fstsw e store status word esc 101 mod 111 r/m sib/disp 15 fclex e clear exceptions esc 011 1110 0010 11 fstenv e store environment esc 001 mod 110 r/m sib/disp 103 104 fldenv e load environment esc 001 mod 100 r/m sib/disp 71 fsave e save state esc 101 mod 110 r/m sib/disp 375 376 frstor e restore state esc 101 mod 100 r/m sib/disp 308 fincstp e increment stack pointer esc 001 1111 0111 21 fdecstp e decrement stack pointer esc 001 1111 0110 22 ffree e free st(i) esc 101 1100 0 st(i) 18 fnop e no operations esc 001 1101 0000 12 shaded areas indicate instructions not available in m8087/m80287. notes: j. these timings hold for operands in the range l x l k q /4. for operands not in this range, up to 76 additional clocks may be needed to reduce the operand. k. 0 s l st(0) l k 2 63 . l. b 1.0 s st(0) s 1.0. m. 0 s st(0) k % , b % k st(1) k a % . n. 0 s l st(0) l k (2 b sqrt(2))/2, b % k st(1) k a % . 39

military i387 tm math coprocessor appendix a compatibility between the m80287 and the m8087 the m80286/m80287 operating in real-address mode will execute m8086/m8087 programs without major modification. however, because of differences in the handling of numeric exceptions by the m80287 npx and the m8087 npx, exception-han- dling routines may need to be changed. this appendix summarizes the differences between the m80287 npx and the m8087 npx, and provides details showing how m8086/m8087 programs can be ported to the m80286/m80287. 1. the npx signals exceptions through a dedicated error line to the m80286. the npx error signal does not pass through an interrupt controller (the m8087 int signal does). therefore, any interrupt- controller-oriented instructions in numeric excep- tion handlers for the m8086/m8087 should be de- leted. 2. the m8087 instructions feni/fneni and fdisi/ fndisi perform no useful function in the m80287. if the m80287 encounters one of these opcodes in its instruction stream, the instruction will effec- tively be ignoredenone of the m80287 internal states will be updated. while m8086/m8087 con- taining these instructions may be executed on the m80286/m80287, it is unlikely that the exception- handling routines containing these instructions will be completely portable to the m80287. 3. interrupt vector 16 must point to the numeric ex- ception handling routine. 4. the esc instruction address saved in the m80287 includes any leading prefixes before the esc opcode. the corresponding address saved in the m8087 does not include leading prefixes. 5. in protected-address mode, the format of the m80287's saved instruction and address pointers is different than for the m8087. the instruction opcode is not saved in protected modeeexcep- tion handlers will have to retrieve the opcode from memory if needed. 6. interrupt 7 will occur in the m80286 when execut- ing esc instructions with either ts (task switched) or em (emulation) of the m80286 msw set (ts e 1orem e 1). if ts is set, then a wait instruction will also cause interrupt 7. an excep- tion handler should be included in m80286/m80287 code to handle these situations. 7. interrupt 9 will occur if the second or subsequent words of a floating-point operand fall outside a segment's size. interrupt 13 will occur if the start- ing address of a numeric operand falls outside a segment's size. an exception handler should be included in m80286/m80287 code to report these programming errors. 8. except for the processor control instructions, all of the m80287 numeric instructions are automati- cally synchronized by the m80286 cpuethe m80286 automatically tests the busy line from the m80287 to ensure that the m80287 has com- pleted its previous instruction before executing the next esc instruction. no explicit wait instruc- tions are required to assure this synchronization. for the m8087 used with m8086 and m8088 proc- essors, explicit waits are required before each numeric instruction to ensure synchronization. al- though m8086/m8087 programs having explicit wait instructions will execute perfectly on the m80286/m80287 without reassembly, these wait instructions are unnecessary. 9. since the m80287 does not require wait instruc- tions before each numeric instruction, the asm286 assembler does not automatically gener- ate these wait instructions. the asm86 assem- bler, however, automatically precedes every esc instruction with a wait instruction. although nu- meric routines generated using the asm86 as- sembler will generally execute correctly on the m80286/m80287, reassembly using asm286 may result in a more compact code image. the processor control instructions for the m80287 may be coded using either a wait or no-wait form of mnemonic. the wait forms of these in- structions cause asm286 to precede the esc in- struction with a cpu wait instruction, in the iden- tical manner as does asm86. a-1

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